Random memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) devices, may lose data stored therein when losing power. Accordingly, various NVM (Nonvolatile Memory) devices have been designed for solving the above mentioned deficiencies of random memory devices. Nowadays, flash memory devices, which are designed based on floating gate, have become the most commonly used NVM devices, because they normally have small cell dimensions and good working performance.
There are basically two major types of NVM devices, stack gate type and split gate type. A stack gate memory device normally includes a tunneling oxide layer formed on a substrate. A floating gate polycrystalline silicon layer is formed on the tunneling oxide layer for storing electrons. A multi-layer stack structure consisting of oxide, nitride and oxide is formed on the floating gate. And a control gate polycrystalline silicon layer is disposed on the multi-layer stack structure, which is adapted to controlling storages and releases of electrons.
Referring to FIG. 1, a split gate memory device is illustrated, which also includes a tunneling oxide layer 11, a floating gate polycrystalline silicon layer 12 for storing electrons, an ONO (oxide-nitride-oxide) stack layer 13, and a control gate polycrystalline silicon layer 14. However, compared with the stack gate memory device, the control gate polycrystalline silicon layer 14 of the split gate memory device is divided into two parts, a first part 141 and a second part 142 as illustrated in FIG. 1. The first part 141 partially covers the floating gate polycrystalline silicon layer 12 and the upper sidewall of the ONO stack layer 13. The second part 142 is located beside the lower sidewall of the stack layer 13. Further, the tunneling oxide layer 11 is located between the control gate polycrystalline silicon layer 14 and the floating gate polycrystalline silicon layer 12. The split gate NVM device further includes a substrate 10, a first oxide layer 15 located between the substrate 10 and the control gate polycrystalline silicon layer 14, and a second oxide layer 16 located between the substrate 10 and the float gate polycrystalline silicon layer 12. The first oxide layer 15 is used for isolating the substrate 10 from the control gate polycrystalline silicon layer 14, and the second oxide layer 16 is used for isolating the substrate 10 from the floating gate polycrystalline silicon layer 12. Compared with stack gate memory devices, split gate memory devices may not have technical drawbacks like excessive writing/erasing.
When writing data into and/or erasing data out from the split gate memory device, a source region and a drain region which have higher electric potentials than a power source electric potential Vcc are used for forming a hot carrier path. Thereafter, electrode carriers can pass through the oxide layer isolating the floating gate from the source region and the drain region. As a result, the electrode carriers may be implanted into the floating gate or be extracted from the floating gate.
However, in practice, the split gate flash memory devices as recited above have some disadvantages. For example, in order to implement an erase operation, a voltage applied is normally larger than 7 V (e.g. 12 V), thus hot electron effect may occur in the channel region. Therefore, after being used for some time, the split gate flash memory devices may have decreased reliabilities, i.e., performance degradation.
In addition, a periphery circuit may be configured to cooperate with the split gate flash memory device to implement some functionality. The periphery circuit is normally a logic circuit which may include logic transistors. If the split gate flash memory device and the transistors are respectively fabricated on different integrated chips, running speed of the entire memory device may be limited by a signal transmission bandwidth between the flash memory device and the periphery circuit. Accordingly, integrated semiconductor device which embeds the logic transistors into the split gate flash memory device is invented.
Referring still to FIG. 1, in the erase operation, a high voltage is applied to the control gate 14. Meanwhile, if the oxide layer 15 does not have an adequate thickness, electrodes in the substrate 10 may be dragged into the control gate 14. Therefore, the gate oxide layer 15 underneath the control gate 14 (specifically, the second part 142 of the control gate 14) is required to have a larger thickness. However, a gate oxide layer of the logic transistor in the periphery circuit is normally not so thick. As a result, when manufacturing the integrated semiconductor device recited above, integration of forming the split gate flash memory device with the thicker oxide layer 15 and forming the logic transistor with the thinner oxide layer is not easy to achieved.
Therefore, there is a need for a new split gate memory device, a new semiconductor device and a manufacturing method thereof.